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Time Predictable Embedded Systems

Budget Code: R-AGR-0741-00
Funding: University of Luxembourg
Start Date: July 1, 2016
End Date: June 30, 2019

Description

In our everyday life, we interact with a huge number of computer systems embedded into larger devices. Examples are phones, cars, home and factory appliances, airplanes and many more. Many of these devices are subject to real-time constraints. Real-time means that the correctness of a system is not only a functional (the right result), but also an extra-functional property (the right result at the right time). Currently, the development of such systems is very challenging as high-level modelling tools only capture the functional behaviour, whereas the timing behaviour simply happens: as the exact timing behaviour depends on the precise target architecture, little to no knowledge about the exact timing is available at an early design-phase.The aim of the project is to re-think the development process of real-time embedded systems and to devise a timing-aware model-driven design process. In stark contrast to the current best-practice approach, we aim at a timing verification already at the modelling level, i.e., right from the start. To lift the timing behaviour from the low-level architecture to the high-level model, we propose to use model interpretation instead of compilation. The model interpreter on the target architecture must provide the same timing behaviour as a model verifier on the host machine, where the high-level model is developed and verified. We refer to this property as timing equivalence. We believe that the strongly simplified and accelerated model development and model verification (including functional verification and timing verification), will outweigh by far the additional overhead due to model interpretation on the target architecture. In the project, we will put this assumption to the test and develop a prototype of the timing-aware model-driven design process.

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