EGERTON – Efficient digital beamforming techniques for onboard digital processors

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Title:  EGERTON – Efficient digital beamforming techniques for onboard digital processors

Funding source: ESA - European Space Agency. (ARTES AT)

Prime Contractor: SnT, University of Luxembourg, Luxembourg

Partners: Thales-Alenia-Space Italy (TAS-I), SES.

Principal investigator: Prof. Symeon Chatzinotas

Researchers:  Dr. Juan Carlos Merlano Duncan (VPI),  Dr. Jorge QuerolDr. Jorge Luis Gonzalez RiosDr. Stavros DomouchtsidisDr. Rakesh Palisetty, Dr. Wallace MartinsDr. Alireza HaqiqtnejadDr. Vu Nguyen Ha.

Starting date / Duration: September 2021 / 24 months

 

Background

Beam Forming is an emerging technology that is currently accumulating considerable interest in satellite communications. Due to the limited onboard power and thermal management challenges, Digital Beam Forming (DBF) of a very large amount of bandwidth is not possible. Current processors can only perform digital beamforming on a small portion of the system capacity. The next generation of On-Board Processor (OBP) will provide much higher computational resources. This evolution will allow the implementation of DBF for a much bigger system capacity and leveraging the numerous DBF advantages. The most salient of these DBF benefits come from beamforming flexibility in beam assignment, beam steering, beam shape and width, power allocation, improved linearization, software-controlled beamforming process, interference minimization, and digital signal processing techniques incorporation.

 

Objectives

This activity aims to develop and demonstrate efficient digital beamforming algorithms and architectures for SATCOM payloads utilizing digital processors and validate them on a representative digital processor testbed. This activity will develop low-complexity, highly efficient algorithms, processing techniques, and architectures to significantly reduce power consumption, mass, and volume and improve integration efficiency. Mathematical techniques combined with spatial symmetry of beams and spatial symmetry of radiating elements will be exploited to reduce the processing to a simple set of additions/subtractions, in many cases entirely avoiding multiplication operations. A representative processor testbed will be developed and used to implement and test the developed algorithms and processing techniques. 

The targeted reduction of power consumption is equal to 50% compared to current digital beamforming implementations. The targeted reduction of the number of ASIC/FPGA components is also equal to 50%. This targeted improvement is an enabling technology development to increase the readiness to implement highly flexible, high-capacity digital payloads based on large array antennas. The target Technology Readiness Level (TRL) for this activity is 4, starting from TRL equal to 2.

 

Challenges

The main challenge of the project is to find novel signal processing algorithms that reduce the costs, complexity, and power consumption of the DBF operation on the OBP. This challenge becomes particulary hard for active arrays with thousands of radiating elements, thousands of beams, and bandwidths of several GHz typical in very high throughput satellites (VHTS) systems.

 

System Architecture

The EGERTON demonstrator will be able to emulate the payload and the RX and TX far-field connectivity, injecting simulated traffic load in input and analyzing it on output.

For the far-field connectivity:

  • antennas have to be scalable up to thousands of active elements
  • different technologies of efficient digital beamforming algorithms will be evaluated, focusing on dense-matrix signal processing techniques.
  • coefficient quantization in the beamforming process, narrowband beamforming, wideband beamforming including true-time delay beamforming
  • subband processing for parallel computing in wideband beamforming scenarios.

The figure below shows a general block diagram of the beamforming network for the transmitter case. The three constitutive blocks are a spare-matrix signal processing block, a dense-matrix signal processing block, and the analog interface to the radiating array elements.

 

Related  Projects: 

  • APSIM - Antennas and Signal Processing Techniques for Interference Mitigation in Next Generation Ka Band High Throughput Satellites (see more). 
  • SeMIGod - Spectrum Management and Interference Mitigation in Cognitive Hybrid Satellite Network (see more). 
  • PROSAT - onboard PROcessing techniques for high throughput SATellites (see more). 
  • CoRaSat - Cognitive Radio for Satellite Communication (see more). 
  • SANSA - Shared Access terrestrial - Satellite Backhaul Network enabled by Smart Antennas (see more). 
  • SERENADE - Satellite Precoding Hardware Demonstrator (see more). 
  • LiveSatPreDem – Live Satellite Precoding Demonstration (see more). 
  • CGD - Prototype of a Centralized Broadband Gateway for Precoded Multi-beam Networks (see more). 
  • DISBuS - Dynamic Beam Forming and In-band Signalling for Next-Generation Satellite Systems (see more). 

Contact:

Dr. Juan Carlos Merlano Duncan, Research Scientist